<commit_before>/*************************************************************************
 *
 *  $RCSfile: javaldx.cxx,v $
 *
 *  $Revision: 1.5 $
 *
 *  last change: $Author: hr $ $Date: 2004-07-23 11:49:55 $
 *
 *  The Contents of this file are made available subject to the terms of
 *  either of the following licenses
 *
 *         - GNU Lesser General Public License Version 2.1
 *         - Sun Industry Standards Source License Version 1.1
 *
 *  Sun Microsystems Inc., October, 2000
 *
 *  GNU Lesser General Public License Version 2.1
 *  =============================================
 *  Copyright 2000 by Sun Microsystems, Inc.
 *  901 San Antonio Road, Palo Alto, CA 94303, USA
 *
 *  This library is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU Lesser General Public
 *  License version 2.1, as published by the Free Software Foundation.
 *
 *  This library is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  Lesser General Public License for more details.
 *
 *  You should have received a copy of the GNU Lesser General Public
 *  License along with this library; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 *  MA  02111-1307  USA
 *
 *
 *  Sun Industry Standards Source License Version 1.1
 *  =================================================
 *  The contents of this file are subject to the Sun Industry Standards
 *  Source License Version 1.1 (the "License"); You may not use this file
 *  except in compliance with the License. You may obtain a copy of the
 *  License at http://www.openoffice.org/license.html.
 *
 *  Software provided under this License is provided on an "AS IS" basis,
 *  WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING,
 *  WITHOUT LIMITATION, WARRANTIES THAT THE SOFTWARE IS FREE OF DEFECTS,
 *  MERCHANTABLE, FIT FOR A PARTICULAR PURPOSE, OR NON-INFRINGING.
 *  See the License for the specific provisions governing your rights and
 *  obligations concerning the Software.
 *
 *  The Initial Developer of the Original Code is: Sun Microsystems, Inc.
 *
 *  Copyright: 2000 by Sun Microsystems, Inc.
 *
 *  All Rights Reserved.
 *
 *  Contributor(s): _______________________________________
 *
 *
 ************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "osl/thread.h"
#include "sal/types.h"
#include "rtl/ustring.hxx"
#include "rtl/byteseq.hxx"
#include "jvmfwk/framework.h"

using namespace rtl;

#define OUSTR(x) OUString(RTL_CONSTASCII_USTRINGPARAM( x ))

static sal_Bool hasOption(char* szOption, int argc, char** argv);
static rtl::OString getLD_LIBRARY_PATH(const rtl::ByteSequence & vendorData);
//static sal_Bool printPaths(const OUString& sPathFile);

#define HELP_TEXT    \
"\njavaldx is necessary to make Java work on some UNIX platforms." \
"It prints a string to std out that consists of directories which " \
"have to be included into the LD_LIBRARY_PATH variable.The setting of " \
"the variable usually occurs in a shell script that runs javaldx.\n" \
"The directories are from the chosen java installation. \n" \
"Options are: \n"\
"--help or -h\n"

int main(int argc, char **argv)
{
    if( hasOption("--help",argc, argv) || hasOption("-h", argc, argv))
    {
        fprintf(stdout, HELP_TEXT);// default
        return 0;
    }
    sal_Bool bEnabled = sal_False;
    if (jfw_getEnabled( & bEnabled) != JFW_E_NONE)
    {
        fprintf(stderr,"javaldx failed! \n");
        return -1;
    }

    if (bEnabled == sal_False)
    {
        //Do not do any preparation because that may only slow startup time.
        return 0;
    }

    JavaInfo * pInfo = NULL;
    javaFrameworkError errcode = JFW_E_NONE;
    errcode = jfw_getSelectedJRE( & pInfo);

    if (errcode == JFW_E_INVALID_SETTINGS)
    {
        fprintf(stderr,"javaldx failed. User must select a JRE from options dialog!");
        return -1;
    }
    else if (errcode != JFW_E_NONE)
    {
        fprintf(stderr,"javaldx failed! \n");
        return -1;
    }

    if (pInfo == NULL)
    {
        errcode = jfw_findAndSelectJRE( & pInfo);
        if (errcode == JFW_E_NO_JAVA_FOUND)
        {
            fprintf(stderr,"javaldx: Could not find a Java Runtime Environment! \n");
            return 0;
        }
        else if (errcode != JFW_E_NONE)
        {
            fprintf(stderr,"javaldx failed!\n");
            return -1;
        }
    }

    //Only do something if the sunjavaplugin created this JavaInfo
    rtl::OUString sVendor1(RTL_CONSTASCII_USTRINGPARAM("Sun Microsystems Inc."));
    rtl::OUString sVendor2(RTL_CONSTASCII_USTRINGPARAM("IBM Corporation"));
    rtl::OUString sVendor3(RTL_CONSTASCII_USTRINGPARAM("Blackdown Java-Linux Team"));
    rtl::OUString sVendor4(RTL_CONSTASCII_USTRINGPARAM("Apple Computer, Inc."));
    if ( ! (sVendor1.equals(pInfo->sVendor) == sal_True
            || sVendor2.equals(pInfo->sVendor) == sal_True
            || sVendor3.equals(pInfo->sVendor) == sal_True
            || sVendor4.equals(pInfo->sVendor) == sal_True))
        return 0;

    rtl::OString sPaths = getLD_LIBRARY_PATH(pInfo->arVendorData);
    fprintf(stdout, "%s\n", sPaths.getStr());
    jfw_freeJavaInfo(pInfo);

    return 0;
}

rtl::OString getLD_LIBRARY_PATH(const rtl::ByteSequence & vendorData)
{
    const sal_Unicode* chars = (sal_Unicode*) vendorData.getConstArray();
    sal_Int32 len = vendorData.getLength();
    rtl::OUString sData(chars, len / 2);
    //the runtime lib is on the first line
    sal_Int32 index = 0;
    rtl::OUString aToken = sData.getToken( 1, '\n', index);

    rtl::OString paths =
        rtl::OUStringToOString(aToken, osl_getThreadTextEncoding());
    return paths;
}

static sal_Bool hasOption(char* szOption, int argc, char** argv)
{
    sal_Bool retVal= sal_False;
    for(sal_Int16 i= 1; i < argc; i++)
    {
        if( ! strcmp(argv[i], szOption))
        {
            retVal= sal_True;
            break;
        }
    }
    return retVal;
}

<commit_msg>INTEGRATION: CWS valgrind02 (1.5.14); FILE MERGED 2004/10/11 17:26:26 mhu 1.5.14.1: #i35209# Adapted to use SAL_IMPLEMENT_MAIN_WITH_ARGS() macro instead of plain main() function.<commit_after>/*************************************************************************
 *
 *  $RCSfile: javaldx.cxx,v $
 *
 *  $Revision: 1.6 $
 *
 *  last change: $Author: rt $ $Date: 2004-10-28 16:24:18 $
 *
 *  The Contents of this file are made available subject to the terms of
 *  either of the following licenses
 *
 *         - GNU Lesser General Public License Version 2.1
 *         - Sun Industry Standards Source License Version 1.1
 *
 *  Sun Microsystems Inc., October, 2000
 *
 *  GNU Lesser General Public License Version 2.1
 *  =============================================
 *  Copyright 2000 by Sun Microsystems, Inc.
 *  901 San Antonio Road, Palo Alto, CA 94303, USA
 *
 *  This library is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU Lesser General Public
 *  License version 2.1, as published by the Free Software Foundation.
 *
 *  This library is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  Lesser General Public License for more details.
 *
 *  You should have received a copy of the GNU Lesser General Public
 *  License along with this library; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 *  MA  02111-1307  USA
 *
 *
 *  Sun Industry Standards Source License Version 1.1
 *  =================================================
 *  The contents of this file are subject to the Sun Industry Standards
 *  Source License Version 1.1 (the "License"); You may not use this file
 *  except in compliance with the License. You may obtain a copy of the
 *  License at http://www.openoffice.org/license.html.
 *
 *  Software provided under this License is provided on an "AS IS" basis,
 *  WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING,
 *  WITHOUT LIMITATION, WARRANTIES THAT THE SOFTWARE IS FREE OF DEFECTS,
 *  MERCHANTABLE, FIT FOR A PARTICULAR PURPOSE, OR NON-INFRINGING.
 *  See the License for the specific provisions governing your rights and
 *  obligations concerning the Software.
 *
 *  The Initial Developer of the Original Code is: Sun Microsystems, Inc.
 *
 *  Copyright: 2000 by Sun Microsystems, Inc.
 *
 *  All Rights Reserved.
 *
 *  Contributor(s): _______________________________________
 *
 *
 ************************************************************************/

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "sal/main.h"
#include "sal/types.h"
#include "osl/thread.h"
#include "rtl/ustring.hxx"
#include "rtl/byteseq.hxx"
#include "jvmfwk/framework.h"

using namespace rtl;

#define OUSTR(x) OUString(RTL_CONSTASCII_USTRINGPARAM( x ))

static sal_Bool hasOption(char* szOption, int argc, char** argv);
static rtl::OString getLD_LIBRARY_PATH(const rtl::ByteSequence & vendorData);
//static sal_Bool printPaths(const OUString& sPathFile);

#define HELP_TEXT    \
"\njavaldx is necessary to make Java work on some UNIX platforms." \
"It prints a string to std out that consists of directories which " \
"have to be included into the LD_LIBRARY_PATH variable.The setting of " \
"the variable usually occurs in a shell script that runs javaldx.\n" \
"The directories are from the chosen java installation. \n" \
"Options are: \n"\
"--help or -h\n"

SAL_IMPLEMENT_MAIN_WITH_ARGS(argc, argv)
{
    if( hasOption("--help",argc, argv) || hasOption("-h", argc, argv))
    {
        fprintf(stdout, HELP_TEXT);// default
        return 0;
    }
    sal_Bool bEnabled = sal_False;
    if (jfw_getEnabled( & bEnabled) != JFW_E_NONE)
    {
        fprintf(stderr,"javaldx failed! \n");
        return -1;
    }

    if (bEnabled == sal_False)
    {
        //Do not do any preparation because that may only slow startup time.
        return 0;
    }

    JavaInfo * pInfo = NULL;
    javaFrameworkError errcode = JFW_E_NONE;
    errcode = jfw_getSelectedJRE( & pInfo);

    if (errcode == JFW_E_INVALID_SETTINGS)
    {
        fprintf(stderr,"javaldx failed. User must select a JRE from options dialog!");
        return -1;
    }
    else if (errcode != JFW_E_NONE)
    {
        fprintf(stderr,"javaldx failed! \n");
        return -1;
    }

    if (pInfo == NULL)
    {
        errcode = jfw_findAndSelectJRE( & pInfo);
        if (errcode == JFW_E_NO_JAVA_FOUND)
        {
            fprintf(stderr,"javaldx: Could not find a Java Runtime Environment! \n");
            return 0;
        }
        else if (errcode != JFW_E_NONE)
        {
            fprintf(stderr,"javaldx failed!\n");
            return -1;
        }
    }

    //Only do something if the sunjavaplugin created this JavaInfo
    rtl::OUString sVendor1(RTL_CONSTASCII_USTRINGPARAM("Sun Microsystems Inc."));
    rtl::OUString sVendor2(RTL_CONSTASCII_USTRINGPARAM("IBM Corporation"));
    rtl::OUString sVendor3(RTL_CONSTASCII_USTRINGPARAM("Blackdown Java-Linux Team"));
    rtl::OUString sVendor4(RTL_CONSTASCII_USTRINGPARAM("Apple Computer, Inc."));
    if ( ! (sVendor1.equals(pInfo->sVendor) == sal_True
            || sVendor2.equals(pInfo->sVendor) == sal_True
            || sVendor3.equals(pInfo->sVendor) == sal_True
            || sVendor4.equals(pInfo->sVendor) == sal_True))
        return 0;

    rtl::OString sPaths = getLD_LIBRARY_PATH(pInfo->arVendorData);
    fprintf(stdout, "%s\n", sPaths.getStr());
    jfw_freeJavaInfo(pInfo);

    return 0;
}

rtl::OString getLD_LIBRARY_PATH(const rtl::ByteSequence & vendorData)
{
    const sal_Unicode* chars = (sal_Unicode*) vendorData.getConstArray();
    sal_Int32 len = vendorData.getLength();
    rtl::OUString sData(chars, len / 2);
    //the runtime lib is on the first line
    sal_Int32 index = 0;
    rtl::OUString aToken = sData.getToken( 1, '\n', index);

    rtl::OString paths =
        rtl::OUStringToOString(aToken, osl_getThreadTextEncoding());
    return paths;
}

static sal_Bool hasOption(char* szOption, int argc, char** argv)
{
    sal_Bool retVal= sal_False;
    for(sal_Int16 i= 1; i < argc; i++)
    {
        if( ! strcmp(argv[i], szOption))
        {
            retVal= sal_True;
            break;
        }
    }
    return retVal;
}

<|endoftext|>


<commit_before>#include "Iop_SubSystem.h"
#include "../MemoryStateFile.h"
#include "../MA_MIPSIV.h"
#include "../Ps2Const.h"
#include "../Log.h"
#include "placeholder_def.h"

using namespace Iop;
using namespace std::tr1;
using namespace PS2;

#define LOG_NAME ("iop_subsystem")

#define STATE_CPU       ("iop_cpu")
#define STATE_RAM       ("iop_ram")
#define STATE_SCRATCH   ("iop_scratch")

CSubSystem::CSubSystem() :
m_cpu(MEMORYMAP_ENDIAN_LSBF, 0, 0x1FFFFFFF),
m_executor(m_cpu),
m_bios(NULL),
m_ram(new uint8[IOP_RAM_SIZE]),
m_scratchPad(new uint8[IOP_SCRATCH_SIZE]),
m_spuRam(new uint8[SPU_RAM_SIZE]),
m_dmac(m_ram, m_intc),
m_counters(IOP_CLOCK_FREQ, m_intc),
m_spuCore0(m_spuRam, SPU_RAM_SIZE),
m_spuCore1(m_spuRam, SPU_RAM_SIZE),
m_spu(m_spuCore0),
m_spu2(m_spuCore0, m_spuCore1)
{
	//Read memory map
	m_cpu.m_pMemoryMap->InsertReadMap((0 * IOP_RAM_SIZE), (0 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,    m_ram,								                        0x01);
	m_cpu.m_pMemoryMap->InsertReadMap((1 * IOP_RAM_SIZE), (1 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,								                        0x02);
	m_cpu.m_pMemoryMap->InsertReadMap((2 * IOP_RAM_SIZE), (2 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,								                        0x03);
	m_cpu.m_pMemoryMap->InsertReadMap((3 * IOP_RAM_SIZE), (3 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,								                        0x04);
	m_cpu.m_pMemoryMap->InsertReadMap(0x1F800000,                   0x1F8003FF,                     m_scratchPad,   									        0x05);
    m_cpu.m_pMemoryMap->InsertReadMap(HW_REG_BEGIN,					HW_REG_END,						bind(&CSubSystem::ReadIoRegister, this, PLACEHOLDER_1),	    0x06);

	//Write memory map
	m_cpu.m_pMemoryMap->InsertWriteMap((0 * IOP_RAM_SIZE),   (0 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,											                                0x01);
	m_cpu.m_pMemoryMap->InsertWriteMap((1 * IOP_RAM_SIZE),   (1 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,											                                0x02);
	m_cpu.m_pMemoryMap->InsertWriteMap((2 * IOP_RAM_SIZE),   (2 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,											                                0x03);
	m_cpu.m_pMemoryMap->InsertWriteMap((3 * IOP_RAM_SIZE),   (3 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,											                                0x04);
	m_cpu.m_pMemoryMap->InsertWriteMap(0x1F800000,      0x1F8003FF,                                 m_scratchPad,									                                0x05);
    m_cpu.m_pMemoryMap->InsertWriteMap(HW_REG_BEGIN,	HW_REG_END,		                            bind(&CSubSystem::WriteIoRegister, this, PLACEHOLDER_1, PLACEHOLDER_2),	        0x06);

	//Instruction memory map
	m_cpu.m_pMemoryMap->InsertInstructionMap((0 * IOP_RAM_SIZE), (0 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,						0x01);
	m_cpu.m_pMemoryMap->InsertInstructionMap((1 * IOP_RAM_SIZE), (1 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,						0x02);
	m_cpu.m_pMemoryMap->InsertInstructionMap((2 * IOP_RAM_SIZE), (2 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,						0x03);
	m_cpu.m_pMemoryMap->InsertInstructionMap((3 * IOP_RAM_SIZE), (3 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,						0x04);

	m_cpu.m_pArch = &g_MAMIPSIV;
	m_cpu.m_pAddrTranslator = &CMIPS::TranslateAddress64;

    m_dmac.SetReceiveFunction(4, bind(&CSpuBase::ReceiveDma, &m_spuCore0, PLACEHOLDER_1, PLACEHOLDER_2, PLACEHOLDER_3));
	m_dmac.SetReceiveFunction(8, bind(&CSpuBase::ReceiveDma, &m_spuCore1, PLACEHOLDER_1, PLACEHOLDER_2, PLACEHOLDER_3));
}

CSubSystem::~CSubSystem()
{

}

void CSubSystem::SetBios(CBiosBase* bios)
{
    m_bios = bios;
}

void CSubSystem::SaveState(CZipArchiveWriter& archive)
{
    archive.InsertFile(new CMemoryStateFile(STATE_CPU,      &m_cpu.m_State, sizeof(MIPSSTATE)));
    archive.InsertFile(new CMemoryStateFile(STATE_RAM,      m_ram,          IOP_RAM_SIZE));
    archive.InsertFile(new CMemoryStateFile(STATE_SCRATCH,  m_scratchPad,   IOP_SCRATCH_SIZE));
    m_bios->SaveState(archive);
}

void CSubSystem::LoadState(CZipArchiveReader& archive)
{
    archive.BeginReadFile(STATE_CPU         )->Read(&m_cpu.m_State, sizeof(MIPSSTATE));
    archive.BeginReadFile(STATE_RAM         )->Read(m_ram,          IOP_RAM_SIZE);
    archive.BeginReadFile(STATE_SCRATCH     )->Read(m_scratchPad,   IOP_SCRATCH_SIZE);
    m_bios->LoadState(archive);
}

void CSubSystem::Reset()
{
    memset(m_ram, 0, IOP_RAM_SIZE);
	memset(m_scratchPad, 0, IOP_SCRATCH_SIZE);
	memset(m_spuRam, 0, SPU_RAM_SIZE);
	m_executor.Clear();
	m_cpu.Reset();
	m_spuCore0.Reset();
	m_spuCore1.Reset();
    m_spu.Reset();
    m_spu2.Reset();
	m_counters.Reset();
	m_dmac.Reset();
	m_intc.Reset();
	m_bios = NULL;

    m_cpu.m_Comments.RemoveTags();
    m_cpu.m_Functions.RemoveTags();
}

uint32 CSubSystem::ReadIoRegister(uint32 address)
{
	if(address == 0x1F801814)
	{
		return 0x14802000;
	}
	else if(address >= CSpu::SPU_BEGIN && address <= CSpu::SPU_END)
	{
		return m_spu.ReadRegister(address);
	}
	else if(address >= CDmac::DMAC_ZONE1_START && address <= CDmac::DMAC_ZONE1_END)
	{
		return m_dmac.ReadRegister(address);
	}
	else if(address >= CDmac::DMAC_ZONE2_START && address <= CDmac::DMAC_ZONE2_END)
	{
		return m_dmac.ReadRegister(address);
	}
	else if(address >= CIntc::ADDR_BEGIN && address <= CIntc::ADDR_END)
	{
		return m_intc.ReadRegister(address);
	}
	else if(address >= CRootCounters::ADDR_BEGIN && address <= CRootCounters::ADDR_END)
	{
		return m_counters.ReadRegister(address);
	}
	else if(address >= CSpu2::REGS_BEGIN && address <= CSpu2::REGS_END)
	{
		return m_spu2.ReadRegister(address);
	}
	else
	{
		CLog::GetInstance().Print(LOG_NAME, "Reading an unknown hardware register (0x%0.8X).\r\n", address);
	}
	return 0;
}

uint32 CSubSystem::WriteIoRegister(uint32 address, uint32 value)
{
	if(address >= CDmac::DMAC_ZONE1_START && address <= CDmac::DMAC_ZONE1_END)
	{
		m_dmac.WriteRegister(address, value);
	}
	else if(address >= CSpu::SPU_BEGIN && address <= CSpu::SPU_END)
	{
		m_spu.WriteRegister(address, static_cast<uint16>(value));
	}
	else if(address >= CDmac::DMAC_ZONE2_START && address <= CDmac::DMAC_ZONE2_END)
	{
		m_dmac.WriteRegister(address, value);
	}
	else if(address >= CIntc::ADDR_BEGIN && address <= CIntc::ADDR_END)
	{
		m_intc.WriteRegister(address, value);
	}
	else if(address >= CRootCounters::ADDR_BEGIN && address <= CRootCounters::ADDR_END)
	{
		m_counters.WriteRegister(address, value);
	}
	else if(address >= CSpu2::REGS_BEGIN && address <= CSpu2::REGS_END)
	{
		return m_spu2.WriteRegister(address, value);
	}
	else
	{
		CLog::GetInstance().Print(LOG_NAME, "Writing to an unknown hardware register (0x%0.8X, 0x%0.8X).\r\n", address, value);
	}
	return 0;
}

unsigned int CSubSystem::ExecuteCpu(bool singleStep)
{
	int ticks = 0;
    if(!m_cpu.m_State.nHasException)
    {
		if(m_intc.HasPendingInterrupt())
		{
			m_bios->HandleInterrupt();
        }
    }
	if(!m_cpu.m_State.nHasException)
	{
		int quota = singleStep ? 1 : 500;
		ticks = quota - m_executor.Execute(quota);
		assert(ticks >= 0);
        {
            if(m_bios->IsIdle())
			{
				ticks += (quota * 2);
            }
			else
			{
				CBasicBlock* nextBlock = m_executor.FindBlockAt(m_cpu.m_State.nPC);
				if(nextBlock != NULL && nextBlock->GetSelfLoopCount() > 5000)
				{
					//Go a little bit faster if we're "stuck"
					ticks += (quota * 2);
				}
			}
        }
		if(ticks > 0)
		{
			m_counters.Update(ticks);
			m_bios->CountTicks(ticks);
		}
	}
	if(m_cpu.m_State.nHasException)
	{
		m_bios->HandleException();
	}
	return ticks;
}
<commit_msg>Fixed memory leak in Iop_SubSystem<commit_after>#include "Iop_SubSystem.h"
#include "../MemoryStateFile.h"
#include "../MA_MIPSIV.h"
#include "../Ps2Const.h"
#include "../Log.h"
#include "placeholder_def.h"

using namespace Iop;
using namespace std::tr1;
using namespace PS2;

#define LOG_NAME ("iop_subsystem")

#define STATE_CPU       ("iop_cpu")
#define STATE_RAM       ("iop_ram")
#define STATE_SCRATCH   ("iop_scratch")

CSubSystem::CSubSystem() :
m_cpu(MEMORYMAP_ENDIAN_LSBF, 0, 0x1FFFFFFF),
m_executor(m_cpu),
m_bios(NULL),
m_ram(new uint8[IOP_RAM_SIZE]),
m_scratchPad(new uint8[IOP_SCRATCH_SIZE]),
m_spuRam(new uint8[SPU_RAM_SIZE]),
m_dmac(m_ram, m_intc),
m_counters(IOP_CLOCK_FREQ, m_intc),
m_spuCore0(m_spuRam, SPU_RAM_SIZE),
m_spuCore1(m_spuRam, SPU_RAM_SIZE),
m_spu(m_spuCore0),
m_spu2(m_spuCore0, m_spuCore1)
{
	//Read memory map
	m_cpu.m_pMemoryMap->InsertReadMap((0 * IOP_RAM_SIZE), (0 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,    m_ram,								                        0x01);
	m_cpu.m_pMemoryMap->InsertReadMap((1 * IOP_RAM_SIZE), (1 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,								                        0x02);
	m_cpu.m_pMemoryMap->InsertReadMap((2 * IOP_RAM_SIZE), (2 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,								                        0x03);
	m_cpu.m_pMemoryMap->InsertReadMap((3 * IOP_RAM_SIZE), (3 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,								                        0x04);
	m_cpu.m_pMemoryMap->InsertReadMap(0x1F800000,                   0x1F8003FF,                     m_scratchPad,   									        0x05);
    m_cpu.m_pMemoryMap->InsertReadMap(HW_REG_BEGIN,					HW_REG_END,						bind(&CSubSystem::ReadIoRegister, this, PLACEHOLDER_1),	    0x06);

	//Write memory map
	m_cpu.m_pMemoryMap->InsertWriteMap((0 * IOP_RAM_SIZE),   (0 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,											                                0x01);
	m_cpu.m_pMemoryMap->InsertWriteMap((1 * IOP_RAM_SIZE),   (1 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,											                                0x02);
	m_cpu.m_pMemoryMap->InsertWriteMap((2 * IOP_RAM_SIZE),   (2 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,											                                0x03);
	m_cpu.m_pMemoryMap->InsertWriteMap((3 * IOP_RAM_SIZE),   (3 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,											                                0x04);
	m_cpu.m_pMemoryMap->InsertWriteMap(0x1F800000,      0x1F8003FF,                                 m_scratchPad,									                                0x05);
    m_cpu.m_pMemoryMap->InsertWriteMap(HW_REG_BEGIN,	HW_REG_END,		                            bind(&CSubSystem::WriteIoRegister, this, PLACEHOLDER_1, PLACEHOLDER_2),	        0x06);

	//Instruction memory map
	m_cpu.m_pMemoryMap->InsertInstructionMap((0 * IOP_RAM_SIZE), (0 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,						0x01);
	m_cpu.m_pMemoryMap->InsertInstructionMap((1 * IOP_RAM_SIZE), (1 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,						0x02);
	m_cpu.m_pMemoryMap->InsertInstructionMap((2 * IOP_RAM_SIZE), (2 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,						0x03);
	m_cpu.m_pMemoryMap->InsertInstructionMap((3 * IOP_RAM_SIZE), (3 * IOP_RAM_SIZE) + IOP_RAM_SIZE - 1,	m_ram,						0x04);

	m_cpu.m_pArch = &g_MAMIPSIV;
	m_cpu.m_pAddrTranslator = &CMIPS::TranslateAddress64;

    m_dmac.SetReceiveFunction(4, bind(&CSpuBase::ReceiveDma, &m_spuCore0, PLACEHOLDER_1, PLACEHOLDER_2, PLACEHOLDER_3));
	m_dmac.SetReceiveFunction(8, bind(&CSpuBase::ReceiveDma, &m_spuCore1, PLACEHOLDER_1, PLACEHOLDER_2, PLACEHOLDER_3));
}

CSubSystem::~CSubSystem()
{

}

void CSubSystem::SetBios(CBiosBase* bios)
{
    if(m_bios != NULL)
    {
        delete m_bios;
        m_bios = NULL;
    }
    m_bios = bios;
}

void CSubSystem::SaveState(CZipArchiveWriter& archive)
{
    archive.InsertFile(new CMemoryStateFile(STATE_CPU,      &m_cpu.m_State, sizeof(MIPSSTATE)));
    archive.InsertFile(new CMemoryStateFile(STATE_RAM,      m_ram,          IOP_RAM_SIZE));
    archive.InsertFile(new CMemoryStateFile(STATE_SCRATCH,  m_scratchPad,   IOP_SCRATCH_SIZE));
    m_bios->SaveState(archive);
}

void CSubSystem::LoadState(CZipArchiveReader& archive)
{
    archive.BeginReadFile(STATE_CPU         )->Read(&m_cpu.m_State, sizeof(MIPSSTATE));
    archive.BeginReadFile(STATE_RAM         )->Read(m_ram,          IOP_RAM_SIZE);
    archive.BeginReadFile(STATE_SCRATCH     )->Read(m_scratchPad,   IOP_SCRATCH_SIZE);
    m_bios->LoadState(archive);
}

void CSubSystem::Reset()
{
    memset(m_ram, 0, IOP_RAM_SIZE);
	memset(m_scratchPad, 0, IOP_SCRATCH_SIZE);
	memset(m_spuRam, 0, SPU_RAM_SIZE);
	m_executor.Clear();
	m_cpu.Reset();
	m_spuCore0.Reset();
	m_spuCore1.Reset();
    m_spu.Reset();
    m_spu2.Reset();
	m_counters.Reset();
	m_dmac.Reset();
	m_intc.Reset();
    SetBios(NULL);

    m_cpu.m_Comments.RemoveTags();
    m_cpu.m_Functions.RemoveTags();
}

uint32 CSubSystem::ReadIoRegister(uint32 address)
{
	if(address == 0x1F801814)
	{
		return 0x14802000;
	}
	else if(address >= CSpu::SPU_BEGIN && address <= CSpu::SPU_END)
	{
		return m_spu.ReadRegister(address);
	}
	else if(address >= CDmac::DMAC_ZONE1_START && address <= CDmac::DMAC_ZONE1_END)
	{
		return m_dmac.ReadRegister(address);
	}
	else if(address >= CDmac::DMAC_ZONE2_START && address <= CDmac::DMAC_ZONE2_END)
	{
		return m_dmac.ReadRegister(address);
	}
	else if(address >= CIntc::ADDR_BEGIN && address <= CIntc::ADDR_END)
	{
		return m_intc.ReadRegister(address);
	}
	else if(address >= CRootCounters::ADDR_BEGIN && address <= CRootCounters::ADDR_END)
	{
		return m_counters.ReadRegister(address);
	}
	else if(address >= CSpu2::REGS_BEGIN && address <= CSpu2::REGS_END)
	{
		return m_spu2.ReadRegister(address);
	}
	else
	{
		CLog::GetInstance().Print(LOG_NAME, "Reading an unknown hardware register (0x%0.8X).\r\n", address);
	}
	return 0;
}

uint32 CSubSystem::WriteIoRegister(uint32 address, uint32 value)
{
	if(address >= CDmac::DMAC_ZONE1_START && address <= CDmac::DMAC_ZONE1_END)
	{
		m_dmac.WriteRegister(address, value);
	}
	else if(address >= CSpu::SPU_BEGIN && address <= CSpu::SPU_END)
	{
		m_spu.WriteRegister(address, static_cast<uint16>(value));
	}
	else if(address >= CDmac::DMAC_ZONE2_START && address <= CDmac::DMAC_ZONE2_END)
	{
		m_dmac.WriteRegister(address, value);
	}
	else if(address >= CIntc::ADDR_BEGIN && address <= CIntc::ADDR_END)
	{
		m_intc.WriteRegister(address, value);
	}
	else if(address >= CRootCounters::ADDR_BEGIN && address <= CRootCounters::ADDR_END)
	{
		m_counters.WriteRegister(address, value);
	}
	else if(address >= CSpu2::REGS_BEGIN && address <= CSpu2::REGS_END)
	{
		return m_spu2.WriteRegister(address, value);
	}
	else
	{
		CLog::GetInstance().Print(LOG_NAME, "Writing to an unknown hardware register (0x%0.8X, 0x%0.8X).\r\n", address, value);
	}
	return 0;
}

unsigned int CSubSystem::ExecuteCpu(bool singleStep)
{
	int ticks = 0;
    if(!m_cpu.m_State.nHasException)
    {
		if(m_intc.HasPendingInterrupt())
		{
			m_bios->HandleInterrupt();
        }
    }
	if(!m_cpu.m_State.nHasException)
	{
		int quota = singleStep ? 1 : 500;
		ticks = quota - m_executor.Execute(quota);
		assert(ticks >= 0);
        {
            if(m_bios->IsIdle())
			{
				ticks += (quota * 2);
            }
			else
			{
				CBasicBlock* nextBlock = m_executor.FindBlockAt(m_cpu.m_State.nPC);
				if(nextBlock != NULL && nextBlock->GetSelfLoopCount() > 5000)
				{
					//Go a little bit faster if we're "stuck"
					ticks += (quota * 2);
				}
			}
        }
		if(ticks > 0)
		{
			m_counters.Update(ticks);
			m_bios->CountTicks(ticks);
		}
	}
	if(m_cpu.m_State.nHasException)
	{
		m_bios->HandleException();
	}
	return ticks;
}
<|endoftext|>


<commit_before>/*

Copyright (c) 2007-2014, Arvid Norberg
All rights reserved.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:

    * Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    * Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in
      the documentation and/or other materials provided with the distribution.
    * Neither the name of the author nor the names of its
      contributors may be used to endorse or promote products derived
      from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

*/

#include "libtorrent/assert.hpp"
#include "libtorrent/puff.hpp"

#include <vector>
#include <string>

namespace
{
	enum
	{
		FTEXT = 0x01,
		FHCRC = 0x02,
		FEXTRA = 0x04,
		FNAME = 0x08,
		FCOMMENT = 0x10,
		FRESERVED = 0xe0,

		GZIP_MAGIC0 = 0x1f,
		GZIP_MAGIC1 = 0x8b
	};

}

namespace libtorrent
{
	// returns -1 if gzip header is invalid or the header size in bytes
	int gzip_header(const char* buf, int size)
	{
		TORRENT_ASSERT(buf != 0);

		const unsigned char* buffer = reinterpret_cast<const unsigned char*>(buf);
		const int total_size = size;

		// The zip header cannot be shorter than 10 bytes
		if (size < 10 || buf == 0) return -1;

		// check the magic header of gzip
		if ((buffer[0] != GZIP_MAGIC0) || (buffer[1] != GZIP_MAGIC1)) return -1;

		int method = buffer[2];
		int flags = buffer[3];

		// check for reserved flag and make sure it's compressed with the correct metod
		if (method != 8 || (flags & FRESERVED) != 0) return -1;

		// skip time, xflags, OS code
		size -= 10;
		buffer += 10;

		if (flags & FEXTRA)
		{
			int extra_len;

			if (size < 2) return -1;

			extra_len = (buffer[1] << 8) | buffer[0];

			if (size < (extra_len+2)) return -1;
			size -= (extra_len + 2);
			buffer += (extra_len + 2);
		}

		if (flags & FNAME)
		{
			while (size && *buffer)
			{
				--size;
				++buffer;
			}
			if (!size || *buffer) return -1;

			--size;
			++buffer;
		}

		if (flags & FCOMMENT)
		{
			while (size && *buffer)
			{
				--size;
				++buffer;
			}
			if (!size || *buffer) return -1;

			--size;
			++buffer;
		}

		if (flags & FHCRC)
		{
			if (size < 2) return -1;

			size -= 2;
//			buffer += 2;
		}

		return total_size - size;
	}

	// TODO: 2 it would be nice to use proper error handling here
	bool inflate_gzip(
		char const* in
		, int size
		, std::vector<char>& buffer
		, int maximum_size
		, std::string& error)
	{
		TORRENT_ASSERT(maximum_size > 0);

		int header_len = gzip_header(in, size);
		if (header_len < 0)
		{
			error = "invalid gzip header";
			return true;
		}

		// start off with 4 kilobytes and grow
		// if needed
		boost::uint32_t destlen = 4096;
		int ret = 0;
		boost::uint32_t srclen = size - header_len;
		in += header_len;

		do
		{
			TORRENT_TRY {
				buffer.resize(destlen);
			} TORRENT_CATCH(std::exception& e) {
				error = "out of memory";
				return true;
			}

			ret = puff((unsigned char*)&buffer[0], &destlen, (unsigned char*)in, &srclen);

			// if the destination buffer wasn't large enough, double its
			// size and try again. Unless it's already at its max, in which
			// case we fail
			if (ret == 1) // 1:  output space exhausted before completing inflate
			{
				if (destlen == maximum_size)
				{
					error = "inflated data too big";
					return true;
				}

				destlen *= 2;
				if (destlen > maximum_size)
					destlen = maximum_size;
			}
		} while (ret == 1);

		if (ret != 0)
		{
			error = "error while inflating data";
			return true;
		}

		if (destlen > buffer.size())
		{
			error = "internal gzip error";
			return true;
		}

		buffer.resize(destlen);

		return false;
	}

}

<commit_msg>fix inflate_gzip export for unit test<commit_after>/*

Copyright (c) 2007-2014, Arvid Norberg
All rights reserved.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:

    * Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    * Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in
      the documentation and/or other materials provided with the distribution.
    * Neither the name of the author nor the names of its
      contributors may be used to endorse or promote products derived
      from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

*/

#include "libtorrent/assert.hpp"
#include "libtorrent/puff.hpp"

#include <vector>
#include <string>

namespace
{
	enum
	{
		FTEXT = 0x01,
		FHCRC = 0x02,
		FEXTRA = 0x04,
		FNAME = 0x08,
		FCOMMENT = 0x10,
		FRESERVED = 0xe0,

		GZIP_MAGIC0 = 0x1f,
		GZIP_MAGIC1 = 0x8b
	};

}

namespace libtorrent
{
	// returns -1 if gzip header is invalid or the header size in bytes
	int gzip_header(const char* buf, int size)
	{
		TORRENT_ASSERT(buf != 0);

		const unsigned char* buffer = reinterpret_cast<const unsigned char*>(buf);
		const int total_size = size;

		// The zip header cannot be shorter than 10 bytes
		if (size < 10 || buf == 0) return -1;

		// check the magic header of gzip
		if ((buffer[0] != GZIP_MAGIC0) || (buffer[1] != GZIP_MAGIC1)) return -1;

		int method = buffer[2];
		int flags = buffer[3];

		// check for reserved flag and make sure it's compressed with the correct metod
		if (method != 8 || (flags & FRESERVED) != 0) return -1;

		// skip time, xflags, OS code
		size -= 10;
		buffer += 10;

		if (flags & FEXTRA)
		{
			int extra_len;

			if (size < 2) return -1;

			extra_len = (buffer[1] << 8) | buffer[0];

			if (size < (extra_len+2)) return -1;
			size -= (extra_len + 2);
			buffer += (extra_len + 2);
		}

		if (flags & FNAME)
		{
			while (size && *buffer)
			{
				--size;
				++buffer;
			}
			if (!size || *buffer) return -1;

			--size;
			++buffer;
		}

		if (flags & FCOMMENT)
		{
			while (size && *buffer)
			{
				--size;
				++buffer;
			}
			if (!size || *buffer) return -1;

			--size;
			++buffer;
		}

		if (flags & FHCRC)
		{
			if (size < 2) return -1;

			size -= 2;
//			buffer += 2;
		}

		return total_size - size;
	}

	// TODO: 2 it would be nice to use proper error handling here
	TORRENT_EXTRA_EXPORT bool inflate_gzip(
		char const* in
		, int size
		, std::vector<char>& buffer
		, int maximum_size
		, std::string& error)
	{
		TORRENT_ASSERT(maximum_size > 0);

		int header_len = gzip_header(in, size);
		if (header_len < 0)
		{
			error = "invalid gzip header";
			return true;
		}

		// start off with 4 kilobytes and grow
		// if needed
		boost::uint32_t destlen = 4096;
		int ret = 0;
		boost::uint32_t srclen = size - header_len;
		in += header_len;

		do
		{
			TORRENT_TRY {
				buffer.resize(destlen);
			} TORRENT_CATCH(std::exception& e) {
				error = "out of memory";
				return true;
			}

			ret = puff((unsigned char*)&buffer[0], &destlen, (unsigned char*)in, &srclen);

			// if the destination buffer wasn't large enough, double its
			// size and try again. Unless it's already at its max, in which
			// case we fail
			if (ret == 1) // 1:  output space exhausted before completing inflate
			{
				if (destlen == maximum_size)
				{
					error = "inflated data too big";
					return true;
				}

				destlen *= 2;
				if (destlen > maximum_size)
					destlen = maximum_size;
			}
		} while (ret == 1);

		if (ret != 0)
		{
			error = "error while inflating data";
			return true;
		}

		if (destlen > buffer.size())
		{
			error = "internal gzip error";
			return true;
		}

		buffer.resize(destlen);

		return false;
	}

}

<|endoftext|>


<commit_before>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C $ */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2017,2019                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
<commit_msg>Adds PDA support<commit_after>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C $ */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2017,2019                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */

///
/// @file pda.C
/// @brief Code to support per-DRAM addressability (PDA)
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: FSP:HB Memory Lab

#include <fapi2.H>
#include <p9_mc_scom_addresses.H>
#include <p9_mc_scom_addresses_fld.H>

#include <generic/memory/lib/utils/c_str.H>
#include <generic/memory/lib/utils/find.H>
#include <lib/ccs/ccs.H>
#include <lib/dimm/mrs_load.H>
#include <lib/dimm/ddr4/mrs_load_ddr4.H>
#include <lib/dimm/ddr4/latch_wr_vref.H>
#include <lib/phy/write_cntrl.H>
#include <lib/phy/dp16.H>
#include <lib/dimm/ddr4/pda.H>
#include <lib/workarounds/ccs_workarounds.H>

namespace mss
{

namespace ddr4
{

namespace pda
{

const std::vector<std::pair<uint64_t, uint64_t>> pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4>::BIT_MAP =
{
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N1},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N3},

    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N1},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N3},

    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N1},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N3},

    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N1},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N3},

    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N1},
};

const std::vector<std::pair<uint64_t, uint64_t>> pdaBitTraits<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8>::BIT_MAP =
{
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2},

    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2},

    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2},

    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2},

    {MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4, MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0},
};

///
/// @brief Helper function for changing the DRAM bit
/// @tparam W the DRAM width
/// @tparam TT the DRAM width traits class
/// @param[in] i_target - the MCA target
/// @param[in] i_dram - the DRAM on which to operate
/// @param[in] i_state - the state to write the bit(s) to
/// @return FAPI2_RC_SUCCESS if and only if ok
///
template< uint8_t W, typename TT = pdaBitTraits<W> >
fapi2::ReturnCode change_dram_bit_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
        const uint64_t i_dram,
        const mss::states& i_state)
{
    fapi2::buffer<uint64_t> l_data;

    // Note: the following avoids "undefined reference to" errors due to the set max dram below
    // The use of traits and a const reference messes with it
    constexpr auto NUM_DRAM = TT::NUM_DRAMS;

    // Check bounds
    FAPI_ASSERT(i_dram < NUM_DRAM,
                fapi2::MSS_PDA_DRAM_OUT_OF_RANGE().
                set_MCA_TARGET(i_target).
                set_DRAM(i_dram).
                set_MAX_DRAM(NUM_DRAM),
                "%s was passed DRAM value of %lu which is not below the max value of %lu",
                mss::c_str(i_target), i_dram, NUM_DRAM);

    FAPI_TRY(mss::getScom(i_target, TT::BIT_MAP[i_dram].first, l_data));
    FAPI_TRY(l_data.writeBit(i_state, TT::BIT_MAP[i_dram].second, TT::NUM_BITS));
    FAPI_TRY(mss::putScom(i_target, TT::BIT_MAP[i_dram].first, l_data));

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Writes the data bit enable for the properly inputted DRAM
/// @param[in] i_target - the MCA target
/// @param[in] i_dram - the DRAM on which to operate
/// @param[in] i_state - the state to write the bit(s) to
/// @return FAPI2_RC_SUCCESS if and only if ok
///
fapi2::ReturnCode change_dram_bit( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
                                   const uint64_t i_dram,
                                   const mss::states& i_state)
{
    uint8_t l_dram_width[MAX_DIMM_PER_PORT] = {0};
    FAPI_TRY(mss::eff_dram_width(i_target, &(l_dram_width[0])), "Failed to get the DRAM's width for %s",
             mss::c_str(i_target));

    {
        const auto& l_dimms = mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target);
        FAPI_ASSERT((l_dram_width[0] == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4) ||
                    (l_dram_width[0] == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8),
                    fapi2::MSS_INVALID_DRAM_WIDTH().
                    set_DIMM_TARGET(l_dimms[0]).
                    set_DRAM_WIDTH(l_dram_width[0]),
                    "%s DRAM width was not x4 or x8 - %lu", mss::c_str(i_target), l_dram_width[0]);
    }

    // We only need to check DIMM 0 due to the plug rules
    // x4 DIMM
    if(l_dram_width[0] == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4)
    {
        FAPI_TRY(change_dram_bit_helper<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4>(i_target, i_dram, i_state));
    }
    // x8 DIMM. The else is ok here as we checked the widths above
    else
    {
        FAPI_TRY(change_dram_bit_helper<fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8>(i_target, i_dram, i_state));
    }

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Configures all DRAM level configuration bits to the inputted settings
/// @param[in] i_target a fapi2::Target MCA
/// @param[in] i_state - OFF_N - 1's, ON_N - 0's
/// @return FAPI2_RC_SUCCESS if and only if ok
/// @note PDA is LOW enable, so 0's means ON. ON will configure the register to 0's - using OFF/ON_N
///
fapi2::ReturnCode blast_dram_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const mss::states& i_state )
{
    typedef mss::dp16Traits<fapi2::TARGET_TYPE_MCA> TT;

    std::vector<fapi2::buffer<uint64_t>> l_reg_data;

    // Gets the register data
    FAPI_TRY(mss::scom_suckah(i_target, TT::DATA_BIT_ENABLE1, l_reg_data));

    // Loops and modifies the data
    for(auto& l_data : l_reg_data)
    {
        // Remember 1 = OFF
        set_dram_enable<DRAM0>(l_data, i_state);
        set_dram_enable<DRAM1>(l_data, i_state);
        set_dram_enable<DRAM2>(l_data, i_state);
        set_dram_enable<DRAM3>(l_data, i_state);
    }

    // Blasts the data back out
    FAPI_TRY(mss::scom_blastah(i_target, TT::DATA_BIT_ENABLE1, l_reg_data));

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Configures PDA timings
/// @param[in] i_target a fapi2::Target MCA
/// @return FAPI2_RC_SUCCESS if and only if ok
///
fapi2::ReturnCode configure_timings( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
{
    // Fun fact, we're hitting all of the bits in this reg, no need for RMW
    fapi2::buffer<uint64_t> l_data;

    // So we want to:
    // 1) Turn on the PDA on MRS bit
    // 2) Have a 0 delay between the MRS being sent and starting the 0/1 latching
    // 3) Hold the delay for as long as possible (safer and easier than figuring out how long to hold the values)
    mss::wc::set_pda_mode(l_data, mss::states::ON);
    mss::wc::set_pda_dq_on_delay(l_data, START_DELAY_VALUE);
    mss::wc::set_pda_dq_off_delay(l_data, HOLD_DELAY_VALUE);

    // Set that reg
    FAPI_TRY(mss::wc::write_config3(i_target, l_data));

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Adds a PDA enable command
/// @param[in] i_target a fapi2::Target DIMM
/// @param[in] i_rank the rank to send to
/// @param[in,out] io_inst the CCS instructions to update
/// @return FAPI2_RC_SUCCESS if and only if ok
///
fapi2::ReturnCode add_enable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
                              const uint64_t i_rank,
                              std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst )
{
    mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err );
    FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS03 data from attributes", mss::c_str(i_target));

    // Overrides the PDA value to be enabled
    l_mrs03.iv_pda = fapi2::ENUM_ATTR_EFF_PER_DRAM_ACCESS_ENABLE;

    FAPI_TRY( mss::mrs_engine(i_target, l_mrs03, i_rank, DELAY, io_inst) );

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Enters into and configures PDA mode
/// @param[in] i_target a fapi2::Target DIMM
/// @param[in] i_rank the rank to send to
/// @return FAPI2_RC_SUCCESS if and only if ok
///
fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
                         const uint64_t i_rank )
{
    ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program;

    const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target);

    FAPI_TRY( add_enable(i_target, i_rank, l_program.iv_instructions) );

    FAPI_TRY( ccs::execute(mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target),
                           l_program,
                           l_mca),
              "unable to execute CCS for MR03 rank %d %s",
              i_rank, mss::c_str(i_target) );

    // Now sets up all of the PDA regs now that we are in PDA mode
    FAPI_TRY(configure_timings(l_mca));
    FAPI_TRY(blast_dram_config(l_mca, mss::states::OFF_N));

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Adds a PDA disable command
/// @param[in] i_target a fapi2::Target DIMM
/// @param[in] i_rank the rank to send to
/// @param[in,out] io_inst the instructions
/// @return FAPI2_RC_SUCCESS if and only if ok
///
fapi2::ReturnCode add_disable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
                               const uint64_t i_rank,
                               std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst )
{
    mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err );
    FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS03 data from attributes", mss::c_str(i_target));

    // Overrides the PDA value to be disabled
    l_mrs03.iv_pda = fapi2::ENUM_ATTR_EFF_PER_DRAM_ACCESS_DISABLE;

    FAPI_TRY( mss::mrs_engine(i_target, l_mrs03, i_rank, DELAY, io_inst) );

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Exits out of and disables PDA mode
/// @param[in] i_target a fapi2::Target DIMM
/// @param[in] i_rank the rank to send to
/// @return FAPI2_RC_SUCCESS if and only if ok
///
fapi2::ReturnCode exit( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
                        const uint64_t i_rank )
{
    ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program;

    const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target);

    // We need everyone to exit PDA mode, so all of them are all ON
    FAPI_TRY(blast_dram_config(l_mca, mss::states::ON_N));

    FAPI_TRY( add_disable(i_target, i_rank, l_program.iv_instructions) );

    FAPI_TRY( mss::ccs::workarounds::exit(i_target, i_rank, l_program) );

    FAPI_TRY( ccs::execute(mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target),
                           l_program,
                           l_mca),
              "unable to execute CCS for MR03 PDA exit rank %d %s",
              i_rank, mss::c_str(i_target) );

    // Disables PDA mode
    {
        fapi2::buffer<uint64_t> l_data;
        FAPI_TRY(mss::wc::read_config3(l_mca, l_data));
        mss::wc::set_pda_mode(l_data, mss::states::OFF);
        FAPI_TRY(mss::wc::write_config3(l_mca, l_data));
    }

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Performs a PDA WR VREF latch
/// @param[in] i_target a fapi2::Target DIMM
/// @param[in] i_rank the rank to send to
/// @param[in] i_mrs the MRS data to update
/// @param[in] i_drams the DRAM to update
/// @return FAPI2_RC_SUCCESS if and only if ok
/// @note A PDA latch of WR VREF settings is the most common PDA operations
/// This function adds a bit of fanciness (compression) to speed up the overall runtime
///
fapi2::ReturnCode execute_wr_vref_latch( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
        const uint64_t i_rank,
        const mss::ddr4::mrs06_data& i_mrs,
        const std::vector<uint64_t>& i_drams )
{
    const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target);

    // If the commands passed in are empty, simply exit
    FAPI_ASSERT((!i_drams.empty()),
                fapi2::MSS_EMPTY_PDA_VECTOR().
                set_PROCEDURE(mss::ffdc_function_codes::PDA_WR_VREF_LATCH_VECTOR),
                "%s PDA commands vector is empty, exiting", mss::c_str(i_target));

    // Enable all individual DRAM
    for(const auto l_dram : i_drams)
    {
        FAPI_TRY(change_dram_bit( l_mca, l_dram, mss::states::ON_N));
    }

    // Issue MRS commands
    {
        ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program;

        FAPI_TRY(mss::ddr4::add_latch_wr_vref_commands( i_target,
                 i_mrs,
                 i_rank,
                 l_program.iv_instructions));

        FAPI_TRY( ccs::execute(mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target),
                               l_program,
                               l_mca),
                  "unable to execute CCS for MR06 rank %d %s",
                  i_rank, mss::c_str(i_target) );
    }

    // Disable all individual DRAM
    for(const auto l_dram : i_drams)
    {
        FAPI_TRY(change_dram_bit( l_mca, l_dram, mss::states::OFF_N));
    }

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Performs a PDA WR VREF latch
/// @param[in] i_commands the PDA commands to issue and DRAM
/// @return FAPI2_RC_SUCCESS if and only if ok
/// @note A PDA latch of WR VREF settings is the most common PDA operations
/// This function adds a bit of fanciness (compression) to speed up the overall runtime
///
fapi2::ReturnCode execute_wr_vref_latch( const commands<mss::ddr4::mrs06_data>& i_commands )
{
    // If the commands passed in are empty, simply exit
    FAPI_ASSERT((!i_commands.empty()),
                fapi2::MSS_EMPTY_PDA_VECTOR().
                set_PROCEDURE(mss::ffdc_function_codes::PDA_WR_VREF_LATCH_CONTAINER),
                "PDA commands map is empty, exiting");

    // Loop until all commands have been issued
    for(const auto& l_commands : i_commands.get())
    {
        // PDA targetting information - stores both the DIMM and rank in a pair
        const auto& l_target_info = l_commands.first;
        const auto& l_dimm = l_target_info.first;
        const auto l_rank = l_target_info.second;

        // The PDA commands consist of MRS's and their associated DRAM's
        const auto& l_pda_commands = l_commands.second;

        // First, enter into PDA mode
        FAPI_TRY(enter(l_dimm, l_rank));

        // Now loops through all of the MRS and DRAM
        for(const auto& l_command : l_pda_commands)
        {
            const auto& l_mrs = l_command.first;
            const auto& l_drams = l_command.second;
            FAPI_TRY(execute_wr_vref_latch( l_dimm,
                                            l_rank,
                                            l_mrs,
                                            l_drams ));
        }

        // Finally, exit out of PDA
        FAPI_TRY(exit(l_dimm, l_rank));
    }

fapi_try_exit:
    return fapi2::current_err;
}

} // ns pda

} // ns ddr4

} // ns mss
<|endoftext|>


<commit_before>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C $          */
/*                                                                        */
/* IBM CONFIDENTIAL                                                       */
/*                                                                        */
/* EKB Project                                                            */
/*                                                                        */
/* COPYRIGHT 2015,2016                                                    */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* The source code for this program is not published or otherwise         */
/* divested of its trade secrets, irrespective of what has been           */
/* deposited with the U.S. Copyright Office.                              */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
//------------------------------------------------------------------------------
/// @file  p9_setup_sbe_config.C
///
/// @brief proc setup sbe config
//------------------------------------------------------------------------------
// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner        : Brian Silver <bsilver@us.ibm.com>
// *HWP Team            : Perv
// *HWP Level           : 2
// *HWP Consumed by     : SBE
//------------------------------------------------------------------------------

//## auto_generated
#include "p9_setup_sbe_config.H"

#include <p9_perv_scom_addresses.H>

enum P9_SETUP_SBE_CONFIG_Private_Constants
{
    ATTR_EQ_GARD_STARTBIT = 0,
    ATTR_EQ_GARD_LENGTH = 6,
    ATTR_EC_GARD_STARTBIT = 8,
    ATTR_EC_GARD_LENGTH = 24,
    ATTR_I2C_BUS_DIV_REF_STARTBIT = 0,
    ATTR_I2C_BUS_DIV_REF_LENGTH = 16,
    ATTR_BOOT_FLAGS_STARTBIT = 0,
    ATTR_BOOT_FLAGS_LENGTH = 32,
    ATTR_PROC_FABRIC_GROUP_ID_STARTBIT = 26,
    ATTR_PROC_FABRIC_GROUP_ID_LENGTH = 3,
    ATTR_PROC_FABRIC_CHIP_ID_STARTBIT = 29,
    ATTR_PROC_FABRIC_CHIP_ID_LENGTH = 3,
    ATTR_BOOT_FREQ_MULT_STARTBIT = 0,
    ATTR_BOOT_FREQ_MULT_LENGTH = 16,
    ATTR_NEST_PLL_BUCKET_STARTBIT = 24,
    ATTR_NEST_PLL_BUCKET_LENGTH = 8

};

fapi2::ReturnCode p9_setup_sbe_config(const
                                      fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
    fapi2::buffer<uint32_t> l_read_scratch_reg = 0;
    fapi2::buffer<uint32_t> l_read_scratch8 = 0;
    fapi2::buffer<uint8_t> l_read_1 = 0;
    fapi2::buffer<uint8_t> l_read_2 = 0;
    fapi2::buffer<uint8_t> l_read_3 = 0;
    fapi2::buffer<uint16_t> l_read_4 = 0;
    fapi2::buffer<uint32_t> l_read_5 = 0;
    fapi2::buffer<uint32_t> l_read_6 = 0;
    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
    FAPI_INF("Entering ...");

    FAPI_DBG("Read Scratch8 for validity of Scratch register");
    //Getting SCRATCH_REGISTER_8 register value
    FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_8_FSI,
                                    l_read_scratch8)); //l_read_scratch8 = CFAM.SCRATCH_REGISTER_8

    //set_scratch1_reg
    {

        FAPI_DBG("Read Scratch_reg1");
        //Getting SCRATCH_REGISTER_1 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_1_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_1

        FAPI_DBG("Reading ATTR_EQ_GARD, ATTR_EC_GARD");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EQ_GARD, i_target_chip, l_read_1));
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_5));

        l_read_1.extractToRight< 0, ATTR_EQ_GARD_LENGTH >(l_read_2);
        l_read_5.extractToRight< 0, ATTR_EC_GARD_LENGTH >(l_read_6);

        l_read_scratch_reg.insertFromRight< ATTR_EQ_GARD_STARTBIT, ATTR_EQ_GARD_LENGTH >(l_read_2);
        l_read_scratch_reg.insertFromRight< ATTR_EC_GARD_STARTBIT, ATTR_EC_GARD_LENGTH >(l_read_6);

        FAPI_DBG("Setting up value of Scratch_reg1");
        //Setting SCRATCH_REGISTER_1 register value
        //CFAM.SCRATCH_REGISTER_1 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_1_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<0>();
    }
    //set_scratch2_reg
    {
        FAPI_DBG("Reading Scratch_reg2");
        //Getting SCRATCH_REGISTER_2 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_2_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_2

        FAPI_DBG("Reading ATTR_I2C_BUS_DIV_REF");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4));

        l_read_scratch_reg.insertFromRight< ATTR_I2C_BUS_DIV_REF_STARTBIT, ATTR_I2C_BUS_DIV_REF_LENGTH >(l_read_4);

        FAPI_DBG("Setting up value of Scratch_reg2");
        //Setting SCRATCH_REGISTER_2 register value
        //CFAM.SCRATCH_REGISTER_2 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_2_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<1>();
    }
    //set_scratch3_reg
    {
        FAPI_DBG("Reading Scratch_reg3");
        //Getting SCRATCH_REGISTER_3 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_3_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_3

        FAPI_DBG("Reading the BOOT_FLAGS");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FLAGS, FAPI_SYSTEM, l_read_5));

        l_read_scratch_reg.insertFromRight< ATTR_BOOT_FLAGS_STARTBIT, ATTR_BOOT_FLAGS_LENGTH >(l_read_5);

        FAPI_DBG("Setting up value of Scratch_reg3");
        //Setting SCRATCH_REGISTER_3 register value
        //CFAM.SCRATCH_REGISTER_3 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_3_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<2>();
    }
    //set_scratch4_reg
    {
        FAPI_DBG("Reading Scratch_reg4");
        //Getting SCRATCH_REGISTER_4 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_4_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_4

        FAPI_DBG("Reading ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4));
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1));

        l_read_scratch_reg.insertFromRight< ATTR_BOOT_FREQ_MULT_STARTBIT, ATTR_BOOT_FREQ_MULT_LENGTH >(l_read_4);
        l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1);

        FAPI_DBG("Setting up value of Scratch_reg4");
        //Setting SCRATCH_REGISTER_4 register value
        //CFAM.SCRATCH_REGISTER_4 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_4_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<3>();
    }
    //set_scratch5_reg
    {
        FAPI_DBG("Reading Scratch_reg5");
        //Getting SCRATCH_REGISTER_5 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_5_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_5

        FAPI_DBG("Reading the control flags : SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_read_1));
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_read_2));
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM,
                               l_read_3));

        l_read_scratch_reg.writeBit<0>(l_read_1.getBit<7>());
        l_read_scratch_reg.writeBit<1>(l_read_3.getBit<7>());
        l_read_scratch_reg.writeBit<2>(l_read_2.getBit<7>());

        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM,
                               l_read_1));

        l_read_scratch_reg.writeBit<3>(l_read_1.getBit<7>());

        FAPI_DBG("Setting up value of Scratch_reg5");
        //Setting SCRATCH_REGISTER_5 register value
        //CFAM.SCRATCH_REGISTER_5 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_5_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<4>();
    }
    //set_scratch6_reg
    {
        FAPI_DBG("Reading Scratch_reg6");
        //Getting SCRATCH_REGISTER_6 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_6_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_6

        FAPI_DBG("Reading attribute for Hostboot slave bit");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target_chip,
                               l_read_1));

        l_read_scratch_reg.writeBit<24>(l_read_1.getBit<7>());

        FAPI_DBG("Reading ATTR_PROC_FABRIC_GROUP and CHIP_ID");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target_chip,
                               l_read_1));
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target_chip,
                               l_read_2));

        l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_GROUP_ID_STARTBIT, ATTR_PROC_FABRIC_GROUP_ID_LENGTH >(l_read_1);
        l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_CHIP_ID_STARTBIT, ATTR_PROC_FABRIC_CHIP_ID_LENGTH >(l_read_2);

        FAPI_DBG("Setting up value of Scratch_reg6");
        //Setting SCRATCH_REGISTER_6 register value
        //CFAM.SCRATCH_REGISTER_6 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_6_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<5>();
    }
    FAPI_DBG("Setting Scratch8 for validity of Scratch register");
    //Setting SCRATCH_REGISTER_8 register value
    //CFAM.SCRATCH_REGISTER_8 = l_read_scratch8
    FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_8_FSI,
                                    l_read_scratch8));

    FAPI_INF("Exiting ...");

fapi_try_exit:
    return fapi2::current_err;

}
<commit_msg>Level 2 HWP for p9_setup_sbe_config<commit_after>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C $          */
/*                                                                        */
/* IBM CONFIDENTIAL                                                       */
/*                                                                        */
/* EKB Project                                                            */
/*                                                                        */
/* COPYRIGHT 2015,2016                                                    */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* The source code for this program is not published or otherwise         */
/* divested of its trade secrets, irrespective of what has been           */
/* deposited with the U.S. Copyright Office.                              */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
//------------------------------------------------------------------------------
/// @file  p9_setup_sbe_config.C
///
/// @brief proc setup sbe config
//------------------------------------------------------------------------------
// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner        : Brian Silver <bsilver@us.ibm.com>
// *HWP Team            : Perv
// *HWP Level           : 2
// *HWP Consumed by     : SBE
//------------------------------------------------------------------------------

//## auto_generated
#include "p9_setup_sbe_config.H"

#include <p9_perv_scom_addresses.H>

enum P9_SETUP_SBE_CONFIG_Private_Constants
{
    ATTR_EQ_GARD_STARTBIT = 0,
    ATTR_EQ_GARD_LENGTH = 6,
    ATTR_EC_GARD_STARTBIT = 8,
    ATTR_EC_GARD_LENGTH = 24,
    ATTR_I2C_BUS_DIV_REF_STARTBIT = 0,
    ATTR_I2C_BUS_DIV_REF_LENGTH = 16,
    ATTR_BOOT_FLAGS_STARTBIT = 0,
    ATTR_BOOT_FLAGS_LENGTH = 32,
    ATTR_PROC_FABRIC_GROUP_ID_STARTBIT = 26,
    ATTR_PROC_FABRIC_GROUP_ID_LENGTH = 3,
    ATTR_PROC_FABRIC_CHIP_ID_STARTBIT = 29,
    ATTR_PROC_FABRIC_CHIP_ID_LENGTH = 3,
    ATTR_BOOT_FREQ_MULT_STARTBIT = 0,
    ATTR_BOOT_FREQ_MULT_LENGTH = 16,
    ATTR_NEST_PLL_BUCKET_STARTBIT = 24,
    ATTR_NEST_PLL_BUCKET_LENGTH = 8

};

fapi2::ReturnCode p9_setup_sbe_config(const
                                      fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
    fapi2::buffer<uint32_t> l_read_scratch_reg = 0;
    fapi2::buffer<uint32_t> l_read_scratch8 = 0;
    fapi2::buffer<uint8_t> l_read_1 = 0;
    fapi2::buffer<uint8_t> l_read_2 = 0;
    fapi2::buffer<uint8_t> l_read_3 = 0;
    fapi2::buffer<uint16_t> l_read_4 = 0;
    fapi2::buffer<uint32_t> l_read_5 = 0;
    fapi2::buffer<uint32_t> l_read_6 = 0;
    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
    FAPI_INF("Entering ...");

    FAPI_DBG("Read Scratch8 for validity of Scratch register");
    //Getting SCRATCH_REGISTER_8 register value
    FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_8_FSI,
                                    l_read_scratch8)); //l_read_scratch8 = CFAM.SCRATCH_REGISTER_8

    //set_scratch1_reg
    {

        FAPI_DBG("Read Scratch_reg1");
        //Getting SCRATCH_REGISTER_1 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_1_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_1

        FAPI_DBG("Reading ATTR_EQ_GARD, ATTR_EC_GARD");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EQ_GARD, i_target_chip, l_read_1));
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_5));

        l_read_1.extractToRight< 0, ATTR_EQ_GARD_LENGTH >(l_read_2);
        l_read_5.extractToRight< 0, ATTR_EC_GARD_LENGTH >(l_read_6);

        l_read_scratch_reg.insertFromRight< ATTR_EQ_GARD_STARTBIT, ATTR_EQ_GARD_LENGTH >(l_read_2);
        l_read_scratch_reg.insertFromRight< ATTR_EC_GARD_STARTBIT, ATTR_EC_GARD_LENGTH >(l_read_6);

        FAPI_DBG("Setting up value of Scratch_reg1");
        //Setting SCRATCH_REGISTER_1 register value
        //CFAM.SCRATCH_REGISTER_1 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_1_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<0>();
    }
    //set_scratch2_reg
    {
        FAPI_DBG("Reading Scratch_reg2");
        //Getting SCRATCH_REGISTER_2 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_2_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_2

        FAPI_DBG("Reading ATTR_I2C_BUS_DIV_REF");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4));

        l_read_scratch_reg.insertFromRight< ATTR_I2C_BUS_DIV_REF_STARTBIT, ATTR_I2C_BUS_DIV_REF_LENGTH >(l_read_4);

        FAPI_DBG("Setting up value of Scratch_reg2");
        //Setting SCRATCH_REGISTER_2 register value
        //CFAM.SCRATCH_REGISTER_2 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_2_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<1>();
    }
    //set_scratch3_reg
    {
        FAPI_DBG("Reading Scratch_reg3");
        //Getting SCRATCH_REGISTER_3 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_3_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_3

        FAPI_DBG("Reading the BOOT_FLAGS");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FLAGS, FAPI_SYSTEM, l_read_5));

        l_read_scratch_reg.insertFromRight< ATTR_BOOT_FLAGS_STARTBIT, ATTR_BOOT_FLAGS_LENGTH >(l_read_5);

        FAPI_DBG("Setting up value of Scratch_reg3");
        //Setting SCRATCH_REGISTER_3 register value
        //CFAM.SCRATCH_REGISTER_3 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_3_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<2>();
    }
    //set_scratch4_reg
    {
        FAPI_DBG("Reading Scratch_reg4");
        //Getting SCRATCH_REGISTER_4 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_4_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_4

        FAPI_DBG("Reading ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4));
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1));

        l_read_scratch_reg.insertFromRight< ATTR_BOOT_FREQ_MULT_STARTBIT, ATTR_BOOT_FREQ_MULT_LENGTH >(l_read_4);
        l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1);

        FAPI_DBG("Setting up value of Scratch_reg4");
        //Setting SCRATCH_REGISTER_4 register value
        //CFAM.SCRATCH_REGISTER_4 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_4_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<3>();
    }
    //set_scratch5_reg
    {
        FAPI_DBG("Reading Scratch_reg5");
        //Getting SCRATCH_REGISTER_5 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_5_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_5

        FAPI_DBG("Reading the control flags : SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_read_1));
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_read_2));
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM,
                               l_read_3));

        l_read_scratch_reg.writeBit<0>(l_read_1.getBit<7>());
        l_read_scratch_reg.writeBit<1>(l_read_3.getBit<7>());
        l_read_scratch_reg.writeBit<2>(l_read_2.getBit<7>());

        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM,
                               l_read_1));

        l_read_scratch_reg.writeBit<3>(l_read_1.getBit<7>());

        FAPI_DBG("Setting up value of Scratch_reg5");
        //Setting SCRATCH_REGISTER_5 register value
        //CFAM.SCRATCH_REGISTER_5 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_5_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<4>();
    }
    //set_scratch6_reg
    {
        FAPI_DBG("Reading Scratch_reg6");
        //Getting SCRATCH_REGISTER_6 register value
        FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_6_FSI,
                                        l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_6

        FAPI_DBG("Reading attribute for Hostboot slave bit");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target_chip,
                               l_read_1));

        if ( l_read_1 )
        {
            l_read_scratch_reg.clearBit<24>();
        }
        else
        {
            l_read_scratch_reg.setBit<24>();
        }

        FAPI_DBG("Reading ATTR_PROC_FABRIC_GROUP and CHIP_ID");
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target_chip,
                               l_read_1));
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target_chip,
                               l_read_2));

        l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_GROUP_ID_STARTBIT, ATTR_PROC_FABRIC_GROUP_ID_LENGTH >(l_read_1);
        l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_CHIP_ID_STARTBIT, ATTR_PROC_FABRIC_CHIP_ID_LENGTH >(l_read_2);

        FAPI_DBG("Setting up value of Scratch_reg6");
        //Setting SCRATCH_REGISTER_6 register value
        //CFAM.SCRATCH_REGISTER_6 = l_read_scratch_reg
        FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_6_FSI,
                                        l_read_scratch_reg));

        l_read_scratch8.setBit<5>();
    }
    FAPI_DBG("Setting Scratch8 for validity of Scratch register");
    //Setting SCRATCH_REGISTER_8 register value
    //CFAM.SCRATCH_REGISTER_8 = l_read_scratch8
    FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_8_FSI,
                                    l_read_scratch8));

    FAPI_INF("Exiting ...");

fapi_try_exit:
    return fapi2::current_err;

}
<|endoftext|>


<commit_before>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_xbus_enable_ridi.H $ */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2017,2019                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
//------------------------------------------------------------------------------
/// @file  p9_xbus_enable_ridi.H
///
/// @brief Enable RI/DI for XBUS
//------------------------------------------------------------------------------
// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner        : Sunil kumar <skumar8j@in.ibm.com>
// *HWP Team            : Perv
// *HWP Level           : 2
// *HWP Consumed by     : HB
//------------------------------------------------------------------------------

#ifndef _P9_XBUS_ENABLE_RIDI_H_
#define _P9_XBUS_ENABLE_RIDI_H_

#include <fapi2.H>

typedef fapi2::ReturnCode (*p9_xbus_enable_ridi_FP_t)(
    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);

/// @brief Drop RI/DI for XBUS
///
/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
/// @return  FAPI2_RC_SUCCESS if success, else error code.

extern "C"
{
    fapi2::ReturnCode p9_xbus_enable_ridi(const
                                          fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
}

#endif
<commit_msg>Update hardware procedure metadata<commit_after>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_xbus_enable_ridi.H $ */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2017,2019                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
//------------------------------------------------------------------------------
/// @file  p9_xbus_enable_ridi.H
///
/// @brief Enable RI/DI for XBUS
//------------------------------------------------------------------------------
// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner        : Sunil kumar <skumar8j@in.ibm.com>
// *HWP Team            : Perv
// *HWP Level           : 3
// *HWP Consumed by     : HB
//------------------------------------------------------------------------------

#ifndef _P9_XBUS_ENABLE_RIDI_H_
#define _P9_XBUS_ENABLE_RIDI_H_

#include <fapi2.H>

typedef fapi2::ReturnCode (*p9_xbus_enable_ridi_FP_t)(
    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);

/// @brief Drop RI/DI for XBUS
///
/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
/// @return  FAPI2_RC_SUCCESS if success, else error code.

extern "C"
{
    fapi2::ReturnCode p9_xbus_enable_ridi(const
                                          fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
}

#endif
<|endoftext|>


<commit_before>/* ConsoleWriter.cpp --
 *
 * Copyright (c) 2014, Lex Chou <lex at chou dot com>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 *   * Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *   * Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *   * Neither the name of Swallow nor the names of its contributors may be used
 *     to endorse or promote products derived from this software without
 *     specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
#include "ConsoleWriter.h"
#include <stdlib.h>
#include <wchar.h>
#include <stdarg.h>
#include <string.h>
#if !defined(_WIN32) && !defined(WIN32)
#include <unistd.h>
#endif
#include <io.h>
#include <stdio.h>

void ConsoleWriter::printf(const wchar_t* fmt, ...)
{
    va_list va;
    va_start(va, fmt);
    vwprintf(fmt, va);
    va_end(va);
}

ConsoleWriter* ConsoleWriter::create()
{
    if(isatty(fileno(stdout)))
    {
        return new AnsiConsoleWriter();
    }
    else
    {
        return new PlainConsoleWriter();
    }

}

void PlainConsoleWriter::setForegroundColor(ConsoleColor color, ConsoleIntensity intensity)
{
}
void PlainConsoleWriter::setBackgroundColor(ConsoleColor color, ConsoleIntensity intensity)
{
}
void PlainConsoleWriter::reset()
{
}

void AnsiConsoleWriter::setForegroundColor(ConsoleColor color, ConsoleIntensity intensity)
{
    printf(L"\x1b[%dm", (intensity == Normal ? 30 : 90) + color);
}
void AnsiConsoleWriter::setBackgroundColor(ConsoleColor color, ConsoleIntensity intensity)
{
    printf(L"\x1b[%dm", (intensity == Normal ? 40 : 100) + color);
}
void AnsiConsoleWriter::reset()
{
    printf(L"\x1b[0m");
}
<commit_msg>Disable ANSI escape codes on win32 platform<commit_after>/* ConsoleWriter.cpp --
 *
 * Copyright (c) 2014, Lex Chou <lex at chou dot com>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 *   * Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *   * Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *   * Neither the name of Swallow nor the names of its contributors may be used
 *     to endorse or promote products derived from this software without
 *     specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
#include "ConsoleWriter.h"
#include <stdlib.h>
#include <wchar.h>
#include <stdarg.h>
#include <string.h>
#if !defined(_WIN32) && !defined(WIN32)
#include <unistd.h>
#else
#include <io.h>
#endif
#include <stdio.h>

void ConsoleWriter::printf(const wchar_t* fmt, ...)
{
    va_list va;
    va_start(va, fmt);
    vwprintf(fmt, va);
    va_end(va);
}

ConsoleWriter* ConsoleWriter::create()
{
#if !defined(_WIN32) && !defined(WIN32)
    if(isatty(fileno(stdout)))
    {
        return new AnsiConsoleWriter();
    }
    else
    {
        return new PlainConsoleWriter();
    }
#else
    return new PlainConsoleWriter();
#endif

}

void PlainConsoleWriter::setForegroundColor(ConsoleColor color, ConsoleIntensity intensity)
{
}
void PlainConsoleWriter::setBackgroundColor(ConsoleColor color, ConsoleIntensity intensity)
{
}
void PlainConsoleWriter::reset()
{
}

void AnsiConsoleWriter::setForegroundColor(ConsoleColor color, ConsoleIntensity intensity)
{
    printf(L"\x1b[%dm", (intensity == Normal ? 30 : 90) + color);
}
void AnsiConsoleWriter::setBackgroundColor(ConsoleColor color, ConsoleIntensity intensity)
{
    printf(L"\x1b[%dm", (intensity == Normal ? 40 : 100) + color);
}
void AnsiConsoleWriter::reset()
{
    printf(L"\x1b[0m");
}
<|endoftext|>